It is well known that electrostatic discharge (ESD) can present a problem in small-scale devices such as integrated circuits (ICs). This is because in an IC having ground and supply pins and pads, an ESD spike on one pin/pad may destroy the entire chip. A number of ways of addressing this problem have been suggested. It is known to provide an IC with circuitry which, in the event of an electrostatic discharge, forms a current discharge path for the ESD current and clamps the voltage of the IC pads at a sufficiently low level to prevent damage to components of the IC. FIGS. 1 and 2 show an example of a known arrangement for providing ESD protection.
FIG. 1 shows, schematically, two circuit blocks 1, 2 of an IC. The blocks 1, 2 may represent respectively analogue and digital circuitry components of the IC and each is assumed to be supplied by a different off-chip supply voltage. In the case of block 1, this supply voltage is Vdd1, and in the case of block 2 the supply voltage is Vdd2. The blocks operate at negative supply voltages Vss1 and Vss2, although in practice both negative supply voltages are ground.
Each block 1, 2 is provided with a series of bonding pads (represented by small square boxes, with the pads of block 1 being shown cross-hatched) that are connected to the pins (not shown) of the IC provided externally of the IC. For each block, at least one of the pads is connected to the positive voltage supply pin (Vdd) and at least one is connected to the negative voltage supply pin (Vss). These pads are referred to collectively hereinafter as “voltage supply” pads. Others of the pads are connected to digital/analogue signal inputs/output pins, clock signal pins, etc. These other pads are referred to hereinafter as “signal” pads.
In order to provide ESD protection, a number of ESD protection rings extend around the entire periphery of the chip. One ring is provided for each Vdd and one for each Vss. Thus, in the example of FIG. 1, four ESD protection rings are provided. Each ring is connected directly to a corresponding one of the voltage supply pins of the IC package. Thus, ring 3 in FIG. 1 is connected to Vdd1, ring 4 to Vss1, ring 5 to Vdd2, and ring 6 to VSS2. Each voltage supply pad is coupled to each ring of the same polarity via ESD protection circuitry that is designed to provide a discharge path should the voltage on a given pad exceed a breakdown voltage (e.g. due to a voltage spike). Each of the signal pads associated with a given block is coupled to both of voltage supply pads of that block via further ESD protection circuitry. Thus, for example, a signal pad of block 1 will be coupled to the voltage supply pads providing Vdd1 and Vss1.
FIG. 2 shows in detail the ESD protection configuration for one block (powered by Vdd1 and Vss1) in the case of a four block IC having respective positive and negative supply voltages (Vdd1 to Vdd4, and Vss1 to Vdd4). Back-to-back diodes are connected between the voltage supply pads Vdd1 and Vss1 and each ESD protection ring of the same polarity. Each ESD protection ring is connected to a pad which is connected directly to the corresponding voltage supply pin (FIG. 2 shows only the pads for Vdd1 and Vss1). It is to be noted that the voltage on the Vdd1 pad cannot be more than the diode forward voltage (nominally 0.7 volts) above or below the voltages on the ESD protection rings of the other positive supply voltages, as one or other of the diodes will turn on and conduct to discharge that pad voltage. The same is true for the Vss1 pad.
It will be appreciated that this ESD protection configuration provides protection not only during operation of an IC, but also during the wire bonding operation during which pads on the chip are bonded to associated pins of the IC package, providing that the first pads to be bonded are the Vsscom and Vddcom pads to which the ESD protection rings are connected. Thereafter, any spike appearing at a voltage supply or signal pad will be conducted through the one or more back-to-back diode pairs to which it is coupled and through one of the ESD protection rings to the connected Vdd or Vss pad.
The need for a pair of ESD protection rails for each unit of a SoC is a significant disadvantage. For example, an SoC having five internal blocks would require five pairs of ESD rings, which potentially increases the size of the chip and creates preferential breakdown mechanisms as some tracks may have lower ohmic paths than others (e.g. if connections are made with different lengths of wiring). A further disadvantage is that the requirement for pairs of back-to-back diodes between each voltage supply pad and each and every other ESD protection ring of the same polarity necessitates a high number of diodes and circuitry connections on the chip, which again can increase the size of the chip and introduce further breakdown mechanisms.